Memory unit test

ABSTRACT

The invention relates to a method and device for operating and/or testing memory units, which make it possible to conduct a time-saving test of semiconductor memories during running operation. The inventive method for testing memory units having storage locations provides that, for the storage locations, a first item of test information is formed according to a variable parameter assigned to the respective storage location and according to the contents of the respective storage location.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is the US National Stage of InternationalApplication No. PCT/DE02/04046, filed Oct. 30, 2002 and claims thebenefit thereof. The International Application claims the benefits ofGerman application No. 10155531.8 filed Nov. 12, 2001 and of Germanapplication No. 10206189.0 filed Feb. 14, 2002, all three of theapplications are incorporated by reference herein in their entirety.

FIELD OF INVENTION

[0002] The invention relates to a method and a device for testing and/oroperating semiconductor memories having storage locations.

[0003] The invention relates to a method and a device for testing and/oroperating semiconductor memories having storage locations, in particularmemory units in error-protected systems, which operate for quite longperiods without interruption. With such error-protected systems hardwareerrors generally have to be detected during running operation.

BACKGROUND OF INVENTION

[0004] Memory units for binary signals are among the most importantfunctional units of digital information processing systems. They areused for example as program and data memory units in digital computers,measuring devices, as code converters and generally for producingcombinational logic circuits. A digital memory unit is an arrangement ofa plurality of storage locations, which are organized so that everystorage location can be accessed from outside. In what is known as aword-organized memory unit all the bits of a word can be addressedsimultaneously and read or input in parallel. In the case of a k-bitword therefore, all the k bits of a word are considered to be a storagelocation. Unless-otherwise stated, a storage location below alwaysrefers to a k-bit long word. When only one bit is addressed at a time,it is referred to as bit organization.

[0005] The former application DE 100 37 992 describes an online testconcept, with which hardware is tested in blocks at regular intervalsduring operation. Time intervals are predefined for this, in which thehardware is tested in cycles and then the original state is restored,before functional operation is continued. The described concept forexample allows online testing of state machines (FSM=Finite StateMachine) and what is known as random logic.

SUMMARY OF INVENTION

[0006] The object of the invention is to make it possible to conduct atime-saving test of semiconductor memories during running operation.

[0007] This object is achieved by a method for testing and/or operatingmemory units with storage locations, with which, for the storagelocations, a first item of test information is formed according to avariable parameter assigned to the respective storage location andaccording to the content of the respective storage location.

[0008] This object is achieved by a device with memory units withstorage locations, whereby the storage locations are each assigned afirst item of test information according to a variable parameterassigned to the respective storage location and according to the contentof the respective storage location.

[0009] The object is based on the knowledge that the effectiveness of amemory unit test can be significantly increased by relatively simplemeasures relating to circuit technology by using a variable parameter toform an item of test information for storage locations. The inventivemethod and the inventive device allow the detection of errors during theaddress, write, store and read processes. Unlike hitherto known memoryunit tests, the time required for the test is proportional to the numberof storage locations n multiplied by m=log₂n and does not increasequadratically with the address space n. As the size of the memory unitincreases, the inventive algorithm can be used very profitably, as thetime required for the test decreases significantly compared withprevious methods, as the memory unit increases, but addressing errorsare still detected.

[0010] In one advantageous embodiment of the invention the memory unittest is carried out in one or a plurality of test cycles. For effectiveerror detection, in particular for the detection of addressing errors,it is proposed that a basic test be carried out across all the storagelocations in the first phase of each test cycle. During the basic testthe content of each of the storage locations is read and the storagelocations are rewritten with this content, extended in each instance toinclude a first item of test information, whereby this first item oftest information is formed according to a variable parameter assigned tothe respective storage location and the previously read content of therespective storage location. In a second phase of the test cycle, afterall storage locations have been read and rewritten according to thefirst phase, the content of the storage locations is read again, asecond item of test information is determined from this content read inthe second phase and the second item of test information is comparedwith the stored first item of test information.

[0011] The first phase of the inventive memory unit test canadvantageously also be used to write and read storage locations todetect errors in the write, read and store processes, in particular todetect coupling errors within a storage location (known as horizontalcoupling errors). The memory unit is returned to the same state asbefore the memory unit test, when, according to a further embodiment ofthe invention, the storage locations are each written with the contentread in the first phase at the end of a basic test cycle of the basictest.

[0012] The above-mentioned variable parameter assigned to a storagelocation can be configured as variable parity. Parity represents thesimplest and, as far as information rate is concerned, the mosteffective coding. One hundred percent of one-bit errors can be detectedwith parity. If the variable parameter is configured as variable parity,an additional bit (known as a parity bit) is formed as the first item oftest information according to the variable parity assigned to therespective storage location and according to the content of therespective storage location. The parity bit is formed so that the totalnumber of one-bits of the content of the respective storage locationextended to include the parity bit is even (in the case of even variableparity) or odd (in the case of odd variable parity). The storagelocation is written in the first phase with the content extended toinclude the parity bit. In the second phase a second item of testinformation is determined from the reread content of the storagelocations and, when variable parity is used, this is configured as avariable parity bit, i.e. as information indicating whether the totalnumber of one-bits of the content read in the second phase is even orodd.

[0013] The inventive method can in particular be used to detect couplingerrors, whereby a coupling error is characterized by the incorrectassignment of one or a plurality of storage locations to a memory unitaddress. Coupling errors can be detected particularly easily, when anumber of test cycles corresponding to the number of address bits of thememory unit address represented in a binary manner is provided and adifferent address bit is used in each test cycle to form a variable itemof test information or variable parity. In order also to detect errors,with which the coupled storage location has a higher address than thecoupling location, it is proposed that in a first segment of a testcycle the storage locations be tested in ascending order according totheir memory unit addresses and in a second segment of the test cyclethe storage locations be tested in descending order according to theirmemory unit addresses.

[0014] If a variable parity is also used in functional operation,software with access to the memory unit would always have to carry theaddress bit defining parity with it and use it to determine currentparity. This problem can be avoided, if during read access to a storagelocation with a memory unit address, a fixed parity bit is formed bymeans of an ex-or link of one parity-defining address bit of therespective memory unit address to the first item of test information ofthe respective storage location and during write access to the storagelocation, the first item of test information is formed by means of anex-or link of the fixed parity bit to the parity-defining address bit.In other words a variable parity bit is used internally but during readaccess a fixed parity is made available externally and during writeaccess the fixed parity supplied by the software is converted internallyto variable parity.

[0015] For hardware with dual-channel architecture the probability oferror detection can be increased, if for testing memory units withstorage locations on at least two different units one access datasignature is formed in each instance and the formed signatures arecompared with each other for error detection.

[0016] The inventive method can advantageously also be used as abuild-in self test (BIST) during production of a memory unit and/orduring the power-on test of a memory unit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The invention is described in more detail and explained belowwith reference to the exemplary embodiments shown in the Figures, inwhich:

[0018]FIG. 1 shows a basic test cycle for testing a storage location,

[0019]FIG. 2 shows a basic test cycle using the example of a 3*k-bitFIFO,

[0020]FIG. 3 shows a hardware architecture for a basic test cycle,

[0021]FIG. 4 shows the formation of an access data signature in adual-channel architecture,

[0022]FIG. 5 shows a scenario of what are known as coupling errors,

[0023]FIG. 6 shows internal data processing during the read process withfixed parity and

[0024]FIG. 7 shows internal data processing during the write processwith fixed parity.

DETAILED DESCRIPTION OF INVENTION

[0025] The individual stages of a method for testing memory units andthe components of a device with memory units are described in moredetail below with reference to the drawings. Unless otherwise stated,the term memory unit is used to refer to static semiconductor memorieshaving random access, also referred to as read-write memory units(RAM=Random Access Memory) and/or read-only memory units (ROM=Read OnlyMemory).

[0026] The incorporation of a memory unit test in an online testrequires a certain amount of time and organization. The pertinentstandards (DIN 19250/19251, DIN 0801, DIN 0801/A1 and IEC 61508) definerequirement classes or require error detection during the followingprocesses:

[0027] Address

[0028] Write

[0029] Store

[0030] Read

[0031] Unlike address errors, the other three types of error (write,store and read) can be detected with relatively simple hardwarestructures and algorithms. In the case of address errors, the detectionof multiple addressing and coupling errors is relatively time-consuming.The other three types of error will therefore be considered first and abasic test concept will be presented for detection of such errors withreference to FIG. 1 and FIG. 2. Additional measures then have to beimplemented depending on the requirements of the required security level(AK or SIL).

[0032]FIG. 1 shows the individual stages 21 to 30 of a basic test cycleof the basic test concept. Within the basic test cycle a storagelocation 1 is tested for errors in the write, store and read processes.The basic test cycle starts with initialization 21 of a FIFO (FIFO=FirstIn First Out memory unit). In the next stage 22 the content of thestorage location 1 to be tested is read and in a further stage 23 saidcontent is stored in a latch 8 (latch=register). In digital technology alatch is understood to mean an arrangement of bistable switchingelements (flip-flops), which are used to receive information, store ittemporarily and then release it again. Unlike the individual RSflip-flop this information may comprise not only one bit but also a dataword with a plurality of bits. In stage 24 the content of the latch 8,the read date, is stored in the FIFO and in stage 25 the output of theFIFO is written into the storage location 1. In the next stage 26 thestorage location 1 is read again and in stage 27 the read date is onceagain written into the latch 8. In stage 28 the read date in the latch 8is compared with the output date of the FIFO. Depending on whether instage 29 the original content of the storage location 1 is restored ornot (as a function of the FIFO depth used), the method now proceedsdirectly to stage 30 or the process is repeated from stage 24. Stage 30comprises the incrementing of the address counter. After incrementingthe address counter indicates the next storage location to be tested ina subsequent basic test cycle, which in turn comprises the correspondingstages 22 to 30. The first stage 21 is superfluous when the basic testcycle is repeated, as the FIFO has already been correctly initialized bycarrying out the previous basic test cycle.

[0033]FIG. 2 shows the process according to FIG. 1 using the example ofa 3*k-bit FIFO 9. For purposes of simplicity a synchronous, static andunidirectional memory unit is considered first, which is organized bybytes (i.e. k=8). FIG. 2 shows a complete basic test cycle 40 for thispurpose, executed within eight individual clock pulses 31 to 38. Eachstorage location 1 can be fully verified in respect of the write, storeand read processes with six memory unit access operations, three writingand three reading. In the case of a k-bit word, all the k bits of a wordare considered to be a storage location. At the end of the test theoriginal location content (i.e. the functional data) is restored. Thewrite date is essentially obtained from the FIFO 9 and the read date istransferred to the FIFO 9. Before the start of the actual test the FIFOis initialized, i.e. the top two FIFO levels are prefilled with thecontents AA'X or 55'X. If k≠8 the top two levels are correspondinglyfilled with the bit patterns “1010 . . . ” Or “0101 . . . ”.

[0034] The lowest level contains a random date ##'X. The storagelocation 1 contains the content SP'X at the start. The suffix 'X here isintended to characterize a hexadecimal number. The entire basic testcycle 40 requires a total of eight clock pulses 31 to 38 to test onestorage location 1. The processes during the individual clock pulses 31to 38 are described below. In the first clock pulse 31 the originalcontent SP'X of the storage location 1 is read and transferred to thelatch 8 at the output of the memory unit 2. The content of the FIFO 9corresponds to initialization. In the second clock pulse 32 the readcontent SP'X is transferred from the latch 8 to the FIFO 9. In the sameclock pulse 32 the output date 55'X of the FIFO 9 is written into thestorage location 1. In the following third clock pulse 33 the lastwritten date 55'X is again read from the storage location and stored inthe latch 8. The read date 55'X is compared with the output date of theFIFO 9 and both should have the same value. The comparison process ismarked in FIG. 2 in each instance with the reference character 42. Inthe fourth clock pulse 34 the read date 55'X is transferred from thelatch 8 to the FIFO 9. The now current output date AA'X of the FIFO 9 isalso written into the storage location 1 in the fourth clock pulse 34.The last written date AA'X is again read from the storage location 1 inthe fifth clock pulse 35 and stored in the latch 8. The value in thelatch 8 is compared with the output date AA'X of the FIFO 9 and bothideally have the same value. In the sixth clock pulse 36 the read dateAA'X is transferred from the latch to the FIFO 9. The output date of theFIFO 9, which now represents the original memory unit content SP'X readfrom the storage location 1 in the first clock pulse 31 is written backinto the storage location 1. The last written date SP'X from the storagelocation is read again in the seventh clock pulse 37 and stored in thelatch 8. The content of the latch 8 is compared with the output dateSP'X of the FIFO 9 and both contain the original date SP'X read fromstorage location 1.

[0035] In the eighth clock pulse 38 the address counter, which addressesthe storage location 1, is finally incremented by one (marked with thereference character 43). The test hardware is now ready to test the nextstorage location (clock pulse 39). The stages listed here can beimplemented relatively easily with a state machine (FSM=Finite StateMachine). Verification of the storage location 1 is actually terminatedin the sixth clock pulse 36 and the original memory unit state restored.In the seventh clock pulse 37 the original memory unit content is readfor the second time and compared with the memory unit content SP'X readin the first clock pulse 31. In this way it is possible to verify nstorage locations in 8*n clock pulses. Here n represents the entireaddress space. With m address bits, n=2m.

[0036]FIG. 3 shows the hardware architecture necessary to test a storagelocation. It shows a memory unit 2, which contains n storage locationseach with k bit. The memory unit 2 has a data input DI, an addressinginput Ad, a trigger or clock input Clk and the inputs Cs, Rd/Wr, whichare provided for accessing the control signals chip select (CS), writeaccess (Wr) and read access (Rd). The memory unit can output data viathe data output DO to a k-bit latch 8. A state machine FSM controls thememory unit test. An individual storage location is addressed via anaddress counter 50. A 3*k-bit FIFO 9 is used to buffer the read data anddata to be read in. The data from the latch 8 and FIFO 9 is comparedusing a comparator 51.

[0037]FIG. 4 shows an exemplary embodiment of a memory system withdual-channel architecture. With dual-channel architecture access datasignatures 5 can also be formed at little cost. A comparison of thesignatures 5 with the access data signatures in the partner ASIC (notshown in FIG. 4) also increases the probability of error detection (seeDE 100 37 992). In addition to the elements already described withreference to FIG. 3, two linear feedback shift registers LFSR 60 arealso required for this. One LFSR 60 is used to form the signature 5 ofthe write data, the other LFSR 60 to form the signature 5 of the readdata of the memory unit. With linear feedback shift registers specificbits of the shift register are fed back to the input via an XNOR gate.

[0038] The method proposed here for testing memory units is particularlysuitable for detecting errors during the address process, particularlyfor detecting what are known as coupling errors. Coupling errors referto unwanted coupling between two or a plurality of storage locations.Coupling error detection is generally very time-consuming and the timerequired for testing increases quadratically with the number of storagelocations n with the hitherto known methods. The test architectureproposed here is simple to set up and can be incorporated easily in thepreviously described online test concept. This means that a securityrequirement up to AK 4 (according to DIN 19250/19251) or SIL 2 to 3(according to IEC 61508) can be achieved. The concept can be used bothwith single-channel and dual-channel architecture.

[0039] Coupling errors between storage locations (known as verticalcoupling errors) are very complex. The known test methods are for thetime being limited to detecting simple coupling errors. FIG. 5 shows atypical scenario of a coupling error. It shows a memory unit 2 withstorage locations 1, 61, which can be accessed via a connection 62. Inthe case of a coupling error the addressed and selected storagelocations are not the same. The addressed storage location is alsoreferred to below as the coupling location and the selected storagelocation as the coupled location. If a first storage location 1 isaddressed but a second storage location 61 is accessed, the firststorage location 1 remains inaccessible, if no further error sourcesexist. Read or write access to the first storage location 1 operates ina formally correct manner but its content is however not touched. Inorder to locate such errors, the entire memory unit is generallyprefilled with a known pattern (e.g. 55'X or AA'X).

[0040] The memory unit content is then inverted address by address andthe entire memory unit is tested for correct data content. Known testsbased on this method are Walkpat and Galpat. The time required fortesting with these methods increases in proportion to the square of thenumber n of storage locations. Methods of this type are not suitable foronline tests, as on the one hand the current memory unit content isdestroyed by the test and on the other hand the test time increasesdrastically with memory unit size and therefore in some circumstances acomplete test of the memory unit cannot be carried out within apredefined time. Coding the data (memory unit content) helps here. Withthe above-mentioned error the date is actually not corrupted but simplyincorrectly assigned. Such errors can only be detected, if the addressis included in the code formation. Parity represents the simplest and,as far as information rate is concerned, the most effective coding. Ahundred percent of one-bit errors can be detected with parity. Theinclusion of parity as one of the coding options for detecting couplingerrors improves the overall situation but it is still unsatisfactory.The effectiveness of parity can however be increased drastically byusing a variable parity VP, e.g. an address-dependent parity. Allcoupling errors of the above-mentioned type can then be detected. Theintroduction of a variable parity VP has the distinct advantage that theaddress does not necessarily have to be included when parity is formed.Error analysis without reference to the address is even simplified andbecomes transparent. With memory units organized by bytes one additionalbit is required (i.e. 12.5% memory unit overhead) or a one bit datareduction from eight to seven. The coupling error is essentiallydetected when the parities of the coupling location and the coupledlocation are different. TABLE 1 MSB LSB Address A3 A2 A1 A0  0 0 0 0 0 1 0 0 0 1  2 0 0 1 0  3 0 0 1 1  4 0 1 0 0  5 0 1 0 1  6 0 1 1 0  7 0 11 1  8 1 0 0 0  9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 141 1 1 0 15 1 1 1 1 Test cycle 1 2 3 4

[0041] For the purposes of clarity the method proposed here will beclarified using the example of a 16-byte memory unit. Four address bitsare required to represent the entire address space of this memory unit.Any storage location can be addressed with a 4-bit counter (e.g. addresscounter 50 in FIG. 3 and FIG. 4). The sixteen states of this counter arecompiled in Table 1. To detect the coupling error fully, each addresspair must be given a different parity at least once.

[0042] The memory unit test is controlled by means of a state machine(FSM). The state machine visits all the addresses from 0 to 15. With thetest described here one of the address bits is used as variable parityVP. In the case in question a maximum of four test cycles then resultswith the cycle-dependent variable parity VP. In the first test cycle thevariable parity VP is derived from MSB (Most Significant Bit), i.e. bitA₃ of the address. In the example, let A₃=‘0’0 be the even parity andA₃=‘1’ be odd parity. As can be seen from Table 1, half of the storagelocations in this test cycle have even parity and the other half haveodd parity. This is the case for all test cycles. In the first testcycle the storage locations of the upper half of the memory unit(addresses 0 to 7) have even parity, while the storage locations of thelower half of the memory unit (addresses 8 to 15) have odd parity. Allcoupling errors considered in pairs, between any address from the uppergroup and any address from the lower group, are always detected. Mutualcoupling errors in the upper half (with A₃=0) or in the lower half (withA₃=1) are not detected. Half of the undetected coupling errors in thetwo ranges are detected in the second test cycle, in which variableparity is represented by the address bit A₂. Half of the hithertoundetected coupling errors are then detected in each further test cycle.In the last test cycle with address bit A₀ (LSB=Least Significant Bit)as variable parity VP all hitherto undetected coupling errors arefinally detected. In this way all coupling errors of the above-mentionedtype are detected in few clock pulses (number of required clock pulsesnot quadratic but simply proportional to the number of storage locationstimes number of address bits) and with less additional hardware.

[0043] The proposed memory unit test therefore comprises two phases. Inthe first phase the basic test described above is carried out. Thestorage locations are thereby verified for the write, read and storeprocesses. This basic test is extended so that the original memory unitcontent written back in the sixth clock pulse 36 is now written backwith the variable parity of the current test cycle according to Table 1.In the second phase, after writing back the entire memory unit withvariable parity with functional data, the memory unit is once again readin full and the parity of the date is compared with the variable parityVP (parity definition by address bit A_((4−i)) in the ith cycle). Thesecond phase only requires two clock pulses per storage location, oneclock pulse for reading and one clock pulse for comparing the date andincrementing the address counter (both tasks could be completed in oneclock period). During the course of the memory unit test as describedabove, the memory unit was processed upwards (starting with the address0). However if the coupled storage location has a higher address thanthe coupling location (see FIG. 5), its date is overwritten once againwith variable parity VP at a later time during the course of phaseprocessing. To detect this coupling error the first and second phaseshave to be repeated again, whereby this time the memory unit isprocessed downwards (starting with the address n). The second phasethereby operates without change. The first phase requires a total of 8*nclock pulses. The second phase requires a further 2*n clock pulses, sothe two phases together require 10*n clock pulses. To process the memoryunits in descending address order it is possible to omit writing andreading the memory unit with the date 55'X and AA'X. In this case thefirst phase can be limited to three clock pulses:

[0044] Reading the current date SP'X (functional date)

[0045] Writing the date with variable parity

[0046] Decrementing the address counter (next address)

[0047] Maximum (3+2)*n=5*n clock pulses are required for the downwardprocessing of the memory unit. Therefore a maximum total of 15*n clockpulses is required for a test cycle with a variable parity pattern,defined by one of the address bits A_(i). One test cycle essentiallycomprises two test runs, i.e. two segments, one with ascending and onewith descending address order. An address space with m address bits,whereby

m=log₂n

[0048] applies, therefore requires maximum (15*n*m) clock pulses intotal.

[0049] For time-critical applications it is possible even to omit thefirst phase completely with test cycles 2 to m. In this case maximum(10*n*m+5*n) clock pulses are required for a full memory unit test. Thismaximum number of (10*n*m+5*n) clock pulses can be reducedsignificantly, if variable parity VP is always used according to themethod described above. In other words parity is defined by therespective address bit A_(i), according to the test cycle, even infunctional operation. In this case the three clock pulses (reading,writing with variable parity and decrementing the address counter) arenot required for the cycle with descending address order. 12*n clockpulses rather than 15*n clock pulses are then required for the firsttest cycle. 4*n clock pulses per cycle are then required for the furthercycles (2*n for the ascending and 2*n for the descending address order,in each instance for the second phase, the first phase is omitted).Therefore a maximum total of (4*n*m=8*n) clock pulses is required for afull memory unit test. The advantage of the faster test run (gainapprox. 60%) must be balanced against higher software costs. Thesoftware in this case must always carry the parity-defining address bitA_(i) with it and use it to determine current parity. This problem canhowever be resolved relatively easily, if a variable parity bit is usedinternally, as described above. However during read access a manipulatedparity bit, which is formed by an ex-or link of A_(i) and the variableparity bit and produces a fixed parity FP (in the case in question evenparity), is made available externally. During write access the paritybit supplied by the software with fixed parity FP (in the case inquestion even parity) is converted internally by an ex-or link with theparity-defining address bit A_(i) to variable parity VP. The parity bitthus obtained is then transferred to the memory unit. Two additionalex-or gates are required for this, as shown in Table 2. TABLE 2Formation of Formation of Date Dx fixed parity variable Parity- DG =even FP (even) parity VP defining parity Variable during read duringwrite address bit Du = odd parity access access A_(i) parity VP FP =A_(i) ⊕ VP VP = A_(i) ⊕ FP 0 Dg 0 0 0 1 Dg 1 0 1 0 Du 1 1 1 1 Du 0 1 0

[0050] If a variable parity VP is always used (even in functional mode),with the basic test concept described above during read access the

[0051] read parity must be compared with the current variable parity,determined by including the parity-defining address bit A_(i). Thiscomparison takes place during all read access operations, except in thefirst clock period of the basis test, as after power-on the memory unitis filled with random data and the parity is invalid. During writeaccess the variable parity VP is formed with the inclusion of theparity-defining address bit A_(i) and transferred to the memory unitwith the date.

[0052]FIG. 6 and FIG. 7 show the hardware required for memory unitaccess in functional operation, if variable parity is always usedinternally. FIG. 6 shows the internal data processing during the readprocess. A date 68 with a variable parity VP is stored in one storagelocation. During read access to this storage location, e.g. by externalsoftware, however it is not the date 68 with variable parity VP that isproduced but the date 65 with a fixed parity FP. A parity-definingaddress bit 10 is selected for this purpose internally, i.e. within thehardware circuit, from the address bits 7 of the memory unit address ofthe respective storage location using a multiplexer MUX. This addressbit 10 is ex-or linked in an ex-or gate 66 to the variable parity bit 63of the date 68. The result of this ex-or link is a fixed parity bit 69,which is used to form the external date 65. The reading softwaretherefore does not see the variable parity VP but can work with dateswith a fixed parity FP.

[0053] In the case of the write process, an external date 65 with afixed parity FP is present and is to be stored in the memory unit in astorage location. A multiplexer MUX is used to select a parity-definingaddress bit 10 from the address bits 7 of the memory unit address of therespective storage location. This address bit 10 is ex-or linked in anex-or gate 67 to the fixed parity bit 64 of the date 65. The result ofthis ex-or link is the variable parity bit 70, which is used to form theinternal date 68. This internal date 68 with the variable parity VP isstored in a storage location. The hardware described with reference toFIG. 6 and FIG. 7 maps the processes described above with reference toTable 2. The parity-defining address bit 10 thereby corresponds to theaddress bit A_(i) mentioned above.

[0054] Advantages of the test method described here are summarized onceagain. The time required for the test increases in proportion to thenumber of storage locations n multiplied by m=log₂n and notquadratically with the address space n as with hitherto known standardtests. Even with a 1 kB memory unit this means a reduction in the numberof clock pulses by the factor one hundred. Instead of 1024 with thehitherto known methods, the multiplicator with the method proposed hereis only log₂1024=10. As the size of the memory unit increases, thealgorithm described here can be used very profitably compared with knownmethods, as the time required for the test decreases exponentially withthe increase in the memory unit. All simple coupling errors of the basictype are detected. The method is also able to detect multiple couplingerrors. The method is simple to carry out and simple to implement andcan therefore also be profitably used for the production test. Thealgorithm proposed here can be interrupted without any problem at anypoint and can therefore be particularly advantageously used in thecontext of the online test concept described above, with which it ispossible to change between test operation and functional operation atany point with this method. The sole disadvantage is that an additionalbit is also required for parity.

[0055] In functional mode the user can choose whether to operate with afixed parity or without parity. In both cases the variable parity isused internally. To carry out a full memory unit test, maximum(4*n*m+8*n) clock pulses are required for a memory unit with n storagelocations. As in both cases the same number of clock pulses is requiredfor a full test, it is recommended that a fixed parity be used. In thiscase a random error occurring during functional operation can bedetected immediately when the memory unit is read.

[0056] For better clarity a synchronous, static and unidirectionalmemory unit was considered in the description. Essentially the methoddescribed here can however be used for any type of memory unit withcorresponding modification. Therefore an asynchronous memory unit can beoperated as a synchronous memory unit by means of a small additionallogic at the inputs or outputs, which supplies the memory unit with data(address, date and control signals) with clock pulse control. With adynamic memory unit it must be ensured that the refresh cycles are takeninto account during the memory unit test. A bi-directional memory unitcan be operated as a unidirectional memory unit by adding an input oroutput latch at the data port. Multiport memory units can be tested withthe same method, whereby the memory unit test is only carried out forindividual ports or consecutively for each port. All the said memoryunits can be in the form of ASICs (Application Specific IntegratedCircuits) or part of such.

[0057] To summarize, the invention therefore relates to a method and adevice for testing and/or operating memory units, which make it possibleto conduct a time-saving test of semiconductor memories during runningoperation. The inventive method for testing memory units 2 havingstorage locations 1 provides that, for the storage locations 1, a firstitem of test information is formed according to a variable parameterassigned to the respective storage location 1 and according to thecontent of the respective storage location 1.

1.-22. (cancelled).
 23. A method for operating and/or testing memoryunits having storage locations, comprising: forming for the storagelocations a first item of test information according to a variableparameter assigned to the respective storage location and according tothe content of the respective storage location.
 24. A method accordingto claim 23, wherein in a first phase of a test cycle: reading thecontent of the storage locations in each instance; forming a first itemof test information for the storage locations according to a variableparameter assigned to the respective storage location and according tothe content of the respective storage location read in the first phase;writing the storage locations with the content read in the first phaseextended in each instance to include the first item of test information;wherein in a second phase of a test cycle: reading the content of thestorage locations to detect errors during the addressing process;forming a second item of test information from the content read in thesecond phase with the inclusion of the variable parameter; and comparingthe second item of test information with the first item of testinformation formed for the respective storage location in the firstphase.
 25. A method according to claim 24, wherein at the end of a basictest cycle of a basic test the storage locations are each written withthe content read in the first phase.
 26. A method according to claim 24,wherein in the first phase storage locations are written and read todetect errors during the write, read and store processes.
 27. A methodaccording to claim 23, wherein for testing memory units having storagelocations one access data signature is formed in each instance on atleast two different units and the signatures formed are compared witheach other for error detection.
 28. A method according to claim 23,wherein the method is used to detect coupling errors, whereby a couplingerror is characterized by the incorrect assignment of one or a pluralityof storage locations to a memory unit address.
 29. A method according toclaim 23, wherein the variable parameter assigned to a storage locationis configured as variable parity.
 30. A method according to claim 23,wherein a number of test cycles corresponding to a number of addressbits of the memory unit address represented in a binary manner isprovided and a different address bit is used in each test cycle to varythe variable parameter.
 31. A method according to claim 30, wherein adifferent address bit is used as variable parity in each test cycle toform the first item of test information.
 32. A method according to claim23, wherein in the first phase of a test cycle at each storage locationof the memory unit: reading and transferring an original content of thestorage location to a register at the output of the memory unit;transferring the read original content from the register to a FIFO andwriting a first output date of the FIFO into the storage location;reading again the content of the storage location, transferring thecontent to the register at the output of the memory unit and comparingthe content with the first output date of the FIFO; transferring theread content from the register to the FIFO and writing a second outputdate of the FIFO into the storage location; reading again the content ofthe storage location, transferring the content to the register at theoutput of the memory unit and comparing the content with the secondoutput date; and transferring the read content from the register to theFIFO and writing the original content from the FIFO into the storagelocation.
 33. A method according to claim 23, wherein in a first segmentof a test cycle the storage locations are tested in ascending orderaccording to their memory unit addresses and in a second segment of thetest cycle the storage locations are tested in descending orderaccording to their memory unit addresses.
 34. A method according toclaim 23, wherein in functional operation during read access to astorage location having a memory unit address a fixed parity bit isformed by an ex-or link of a parity-defining address bit of therespective memory unit address to the first item of test information ofthe respective storage location and during write access to the storagelocation the first item of test information is formed by an ex-or linkof the fixed parity bit to the parity-defining address bit.
 35. A methodaccording to claim 23, wherein the method for testing memory units isprovided within any time segments of functional operation.
 36. A methodaccording to claim 23, wherein the method is used as a build-in selftest during production of a memory unit.
 37. A Device comprising memoryunits having storage locations, wherein the storage locations are eachassigned a first item of test information according to a variableparameter assigned to the respective storage location and the content ofthe respective storage location.
 38. A Device according to claim 37,further comprising: a mechanism for reading the content of the storagelocations; a mechanism for writing the storage locations; a mechanismfor forming a first item of test information according to a variableparameter assigned to the respective storage location and the content ofthe respective storage location read in a first phase of a test cycle; amechanism for forming a second item of test information from the contentread in a second phase of the test cycle; and a mechanism for comparingthe second item of test information with the first item of testinformation formed for the respective storage location in the firstphase.
 39. A Device according to claim 37, wherein for testing memoryunits having storage locations mechanisms for forming and comparingaccess data signatures are provided on at least two different units. 40.A Device according to claim 37, wherein the variable parameter assignedto a storage location is configured as variable parity.
 41. A Deviceaccording to claim 37, wherein the variable parameter assigned to astorage location is configured according to an address bit of the memoryunit address represented in a binary manner.
 42. A Device according toclaim 37, wherein a different address bit is provided in each instanceas variable parity to form the first item of test information in eachtest cycle.
 43. A Device according to claim 37, wherein registers areprovided at the output of the memory unit and a FIFO is provided tobuffer storage location content and output dates.
 44. A Device accordingto claim 37, further comprising: a first ex-or gate to form a fixedparity bit during read access to a storage location having a memory unitaddress by an ex-or link of a parity-defining address bit of therespective memory unit address to the first item of test information ofthe respective storage location; and a second ex-or gate to form thefirst item of test information during write access to the storagelocation by an ex-or link of the fixed parity bit to the parity-definingaddress bit.